1 standard ics 8-bit, serial in, parallel out driver BA829 the BA829 is an 8-bit, serial input, parallel output driver. this is a monolithic ic developed for use in thermal print heads, led character displays, and other similar applications. applications thermal print head drivers led character displays features 1) can drive up to 300ma. 2) controlling the strobe terminal with the drive timing pulse enables current to be reduced when drive is not being carried out. 3) using the data output terminal for the next data input enables secondary connections. 4) the digital ground and power ground are separated. 5) a latch is included between the shift register and driver output. 6) a stand-by function is built in. (10 m a typ. at stand-by) pin assignments 1 2 3 4 5 6 7 8 9 clk psw d out v cc pgnd 08 07 06 05 latch stb data lgnd pgnd 01 02 03 04 18 17 16 15 14 13 12 11 10
2 standard ics BA829 block diagram 13 01 12 02 11 14 17 18 1 16 5 4 15 3 2 03 10 04 9 05 8 06 7 07 6 08 power gnd v cc logic gnd power on psw d out shift reg. latch pgnd stb latch clk data absolute maximum ratings (ta = 25?) parameter symbol limits unit applied voltage v cc 7.0 v power dissipation pd 1100 mw operating temperature topr ? 25 ~ + 70 c storage temperature tstg ? 55 ~ + 125 c input voltage v in ? 0.3 ~ v cc v output voltage v out 15 v
3 standard ics BA829 recommended operating conditions (topr = ?25 to + 70?) parameter min. typ. max. unit conditions v cc 4.5 5.0 5.5 v t clk 500 khz t pset 500 ns t wc 1 m s t dset 300 ns t dhold 400 ns t lt1 600 ns t lt2 250 ns t wl 800 ns t st1 300 ns t st2 300 ns t ws 3 m s 0.2 v v g symbol fig.4 fig.4 fig.4 fig.4 fig.4 fig.4 fig.4 fig.4 fig.4 fig.4 power supply voltage clock frequency power setup time clock pulse width data setup time data hold time latch pulse timing time 1 latch pulse timing time 2 latch pulse width strobe pulse timing time 1 strobe pulse timing time 2 strobe pulse width voltage between gnds * * this is the phase differential between the l-gnd and the p-gnd. shorting should be kept as close to the power supply as possib le, but the range should be such that the phase differential between the l-gnd pin and the p-gnd pin does not exceed 0.2v. electrical characteristics (unless otherwise noted, ta = 25?, v cc = 5.0 v) parameter symbol min. typ. max. unit conditions measurement circuit supply current (1) i cc1 10 20 m a psw "l" fig.1 supply current (2) i cc2 110 158 ma psw "h", stb "h" fig.1 supply current (3) i cc3 14 20 ma psw "h", stb "l" fig.1 output pin on voltage v oon 0.4 0.6 v i oon = 300ma fig.1 output pin leakage current i ooff 10 50 m av o = 13.5v fig.1 data transfer speed f clk 500 khz fig.1 input high level voltage v ih 2.6 v fig.2 input low level voltage v il 0.8 v fig.2 input high level current i ih1 0.1 10 m a v i = 3.4v, clk, latch, data, fig.1 stb pin input low level current i il1 ? 0.01 ? 0.1 ma v i = 0.4v, clk, latch, data, fig.1 stb pin "h" level data output v doh 2.8 3.0 vi doh = ? 400 m a fig.1 "l" level data output v dol 0.3 0.4 v i dol = d 1.6ma fig.1 data output delay time t dlh 0.6 1.0 m sr ld = 10k w data output delay time t dhl 0.6 2.0 m sr ld = 10k w printing output delay time t olh 10 m sr l = 560 w , v o = 13.5v printing output delay time t ohl 10 m sr l = 560 w , v o = 13.5v input high level current i ih2 0.04 0.1 ma v i = 3.4v, psw pin fig.1 input low level current i il2 0.1 10 m av i = 0.4v, psw pin fig.1 voltage voltage
4 standard ics BA829 measurement circuits v v a a v a i cc1 ~ 3 v cc pulse gen. clk data pgnd pgnd lgnd v cc latch stb psw d 0 08 01 v oon v o i l v doff v dch v dcl r ld r l 8 fig.1 a clk data latch stb psw lgnd v cc i ih , i il v i v cc fig.2
5 standard ics BA829 input / output circuits v cc i il (a) input (clk , data , latch , stb ) v cc (b) input (psw) fig.3 v cc i il (c) output (d out ) timing chart t pset t wc t wc t dset t dlh t dhl t lt1 t lt2 t wl t wl t st1 t ws t dhl t dlh t dhold o8 stb latch d out data clk psw 128910 fig.4
6 standard ics BA829 application example stb lat clk psw l ? gnd p ? gnd v cc d in v o 18 17 16 15 14 13 12 11 10 1 2 3 4567 89 18 17 16 15 14 13 12 11 10 1 2 3 4567 89 fig.5
7 standard ics BA829 electrical characteristic curves 400 300 200 100 0 6 121824 output supplied voltage : v o (v) output current : i o (ma) 13.5 fig.6 output supplied voltage vs. output current and range of usdoility t his product should be used within the range indicated by the shaded section above, even if the load includes reactance. 2000 1500 1000 1100 500 0 25 75 125 ambient temperature : ta ( c) power dissipation : pd (mw) fig.7 ambient temperature vs. power dissipation 85% 61% 180ma 90% 55% 46% ta = 70 c ta = 25 c ta = 50 c 400 300 200 100 0 20 40 60 80 100 stb duty (%) output current : i o (ma) fig.8 output duty maximum output current (when all bits are on, duty cycle is 1hz or higher) circuit operation the BA829 has the internal configuration shown in the logic diagram, with the following five input pins: clock (clk), data (data), latch (latch), strobe (stb), and power switch (psw). data input is synchronized to the clock, with data being read serially at the rising edge and latched at the rising edge of the shift register after it has shifted. the latched data appears at output terminals o 1 to o 8 , depending on the strobe input, with that pulse width being the same as that of the strobe input. the data output pin dout is used when ics are con- nected in cascade format, and when the output for the last stage of the shift register appears, is connected to the next data input pin data. when these clock and strobe latches and power switch are used in common, the output pins can be increased by eight bits each. in stand-by mode, the power switch is set to ?? external dimensions (units: mm) dip18 0.51min. 18 10 9 1 6.5 0.3 22.9 0.3 3.29 0.2 0.5 0.1 0.3 0.1 2.54 3.95 0.3 0 ~ 15 7.62
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